Through-Silicon Vias for 3D Integration

Through-Silicon Vias for 3D Integration
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The structure is converted into a unique triaxial via by etching a hole within what was the center post FIG. This results in a three conductor via with 50 a as the inner or signal conductor, 52 as the middle or inner shield conductor and 60 a as the outer shield conductor, all of which are electrically independent of each other. As previously illustrated, the process flow is exactly the same as for the aforementioned coaxial structure.

The main difference resides in a pattern being etched at the beginning of the process. Patterning the structure at the first lithography step with a third recess enables forming a third conductor in the substrate. It is worth noting that additive concentric rings may be added to a fourth and a fifth conductor.

The number of additional conductor rings added is limited by available space on the substrate. The structure thus defined can be manufactured using techniques and materials that are compatible with CMOS technology. In one embodiment of the invention, a desired resist pattern is first created using lithography, It is followed by etching, e. This is followed by a conformal insulator deposition in the range of 0.

This is followed by seed deposition, preferably by Cu ranging from 0. The wafer is then sent through a Cu electroplating bath to deposit plated Cu that covers the walls but does not fill the annular region completely. This is followed by deposition of a second barrier layer, e. The next step consists of depositing a polymer, e.

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The polyimide is preferably cured according to manufacturer specifications. The polymer is then removed from the uppermost surface, preferably using a plasma ash or similar process. The wafer is then back-side thinned to expose the bottom of the TSVs such that they protrude from the back surface. The amount of protrusion should be equal to or be greater than the thickness of the two barrier layers, added to the copper, and added to the via insulating layer.

The next step is to depose an insulator or insulators, e. With the coaxial disclosure, the isolation mentioned above applies only to the outer shield. The isolation to the inner conductor is now defined by the film PSPI that resides between the inner conductor and the outer conductor.


This film can be thicker, i. Furthermore, it is advantageous to employ a lower k value material as the insulating layer that separates the conductors, since this helps reducing the capacitance, and, thereby, allows the signals to travel faster through the TSV. While the present invention has been particularly described in conjunction of a simple illustrative embodiment, it is to be understood that one of ordinary skill in the art that the foregoing and other changes in form and detail may be made therein without departing from the spirit and scope of the invention.

The IC structure as recited in claim 1 further comprises a center post made of the same material as said substrate. The IC structure as recited in claim 1 , wherein said conductive lines are connected to active layers provided with interconnect wires or passive circuitry formed upon said substrate. The IC structure as recited in claim 1 , wherein said conductive lines are respectively connected to a voltage or to ground.

The IC structure as recited in claim 2 , wherein said TSV is an annular via having an inner and an outer wall filled with insulating material deposited on exposed surfaces. The IC structure as recited in claim 5 wherein said insulator outer wall is a dielectric film covering sidewalls of said TSV outer circumference, and wherein said insulator inner wall is a dielectric film covering said central post of said via. The IC structure as recited in claim 5 , wherein said insulating material electrically insulates said substrate from said conductive lines.

The IC as recited in claim 8 , wherein said PSPI is selected from a group consisting of polyimide, benzocyclobutene or fluorinated polyimide, polyorganohydrosilane, polyphenylenes, polysiloxanes, copolymers of divinylsiloxane and bisbenzocyclobutene, polybenzil, polyarylethers and polytetraflurorethylene, and photosensitive polymers. The IC as recited in claim 1 , wherein said center post is filled with polyimide. The IC structure as recited in claim 1 , wherein said TSV topside and backside surfaces are planarized, severing a connection between said conductive lines.

The IC structure as recited in claim 11 , wherein two of said severed conductive lines respectively connected to a voltage and to ground and coupled to said center post form a coaxial TSV.

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The IC structure as recited in claim 1 , wherein three of said conductive lines respectively connected to voltages and to ground and coupled to two center posts form a triaxial TSV. A method of forming an IC TSV on a substrate comprising: i etching at least an annular via within said substrate leaving exposed a central post; conformally forming a dielectric film covering a an outer circumference on an outer circumference of said TSV sidewalls, b an inner circumference covering the sidewall of said central post, and c a dielectric film deposited substantially upon a top surface of an underlying active layer;.

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The method as recited in claim 14 , wherein said filling said remaining via space is performed with a PSPI fill. The method as recited in claim 16 , wherein said step of filling said via is followed by removing any excess polyimide from the top surface while leaving the polyimide inside the via. The method as recited in claim 17 , wherein said removing of said excess polyimide is followed by an ash process. The method as recited in claim 14 , wherein planarizing said front and back surfaces of said substrate leaves said top surfaces of said TSVs separated from each other, while leaving said TSVs remain connected to one another at the respective bottoms of the TSVs.

The method as recited in claim 19 , wherein following the step of planarizing said backside of said substrate removes any protruding portions of said vias, and further removes a bottom portion of said conductive materials in said vias leaving the inner conductor electrically isolated from the outer conductor. CN CNB en USB2 en. CNB en. DEB4 en.

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GBB en. TWIB en. WOA2 en. Wafer-level through-silicon via transmission structure applicable to microwave band and manufacturing method thereof. Through silicon via tsv isolation structures for noise reduction in 3d integrated circuit. High performance on-chip vertical coaxial cable, method of manufacture and design structure. Process and material for preventing deleterious expansion of high aspect ratio copper filled through silicon vias tsvs.

Methods for performing a via reveal etching process for forming through-silicon vias in a substrate. USB1 en. Hybrid conductor through-silicon-via for power distribution and signal transmission. KRA en. Method for forming three-dimensional interconnection, circuit arrangement comprising three-dimensional interconnection, and metal film-forming composition for three-dimensional interconnection.

Implementing integrated circuit chip attach in three dimensional stack using vapor deposited solder Cu pillars. Method of manufacturing cap substrate, method of manufacturing mems device using same, and mems device. Semiconductor devices and semiconductor packages including magnetic shielding layers and methods of manufacturing semiconductor devices and semiconductor packages.

Through-Silicon Vias (TSVs) - Semiconductor Engineering

Coaxial connector feed-through for multi-level interconnected semiconductor wafers. Integrated circuit structure having deep trench capacitor and through-silicon via and method of forming same. Integrated circuits with a resistance to single event upset occurrence and methods for providing the same. Microelectronic device, stacked die package and computing system containing same, method of manufacturing a multi-channel communication pathway in same, and method of enabling electrical communication between components of a stacked-die package.

EPB1 en. Semiconductor device with through-substrate via covered by a solder ball and related method of production. EPA1 en. Semiconductor die with a through silicon via and corresponding manufacturing process.

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Method of making a through electrical connection and a capacitor crossing in a substrate, and corresponding device. High-frequency integrated interconnect structure based on a perspective of the soi tsv. Heavily doped silicon shielding silicon through hole structure and manufacturing method thereof. Wafer three-dimensional integration lead technique and its structure for three-dimensional storage.

Through-chip conductors for low inductance chip-to-chip integration and off-chip connections. Silicon chip carrier with conductive through-vias and method for fabricating same. Lightweight and compact through-silicon via stack package with excellent electrical connections and method for manufacturing the same.

Through silicon via TSV isolation structures for noise reduction in 3D integrated circuit. Process and material for preventing deleterious expansion of high aspect ratio copper filled through silicon vias TSVs. Novel integration process to form microelectronic or micromechanical structures. GBD0 en. TWA en.

Application Example

In electronic engineering, a through-silicon via (TSV) or through-chip via is a vertical electrical connection (via) that passes completely through a silicon wafer or die. TSVs are high performance interconnect techniques used as an alternative to wire-bond and flip chips to create 3D packages and 3D integrated circuits. . In one of the sections titled Through Silicon Vias. Through-Silicon Vias for 3D Integration [John H. Lau] on *FREE* shipping on qualifying offers.

USA1 en. GBA en.

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In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. Ebrahim Ghafar-Zadeh. This work investigates the scaling and microstructure effects on stress and extrusion statistics of TSVs to assess reliability risks for future 3D technology with continued TSV downscaling. Typical electronic systems may comprise a variety of electronic components fabricated specifically for a particular function. The next step consists of depositing a polymer, e.

DET5 en. WOA3 en. CNA en. Interposer may be formed from any suitable material, such as any material conventionally used to form an interposer. Suitable materials include silicon and other electrically insulating materials.